The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a ferroelectric memory device.
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its only supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture effects the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
In a 1T/1C FeRAM cell there is one transistor and one storage capacitor. The bottom electrode of the storage capacitor is connected to the drain of the transistor. The 1T/1C cell is read from by applying a signal to the gate of the transistor (wordline) thereby connecting the bottom electrode of the capacitor to the source of the transistor (bitline). A pulse signal is then applied to the top electrode contact (plate line or drive line). The potential on the bitline of the transistor is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier is connected to the bitline and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell must be rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
A 2T/2C memory cell in a memory array couples to a bit line (xe2x80x9cbitlinexe2x80x9d) and the inverse of the bit line (xe2x80x9cbitline-barxe2x80x9d) that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors and two ferroelectric capacitors. A first transistor couples between the bitline and a first capacitor. A second transistor couples between the bitline-bar and a second capacitor. The first and second capacitors have a common terminal or plate to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors of the dual capacitor ferroelectric memory cell are enabled to couple the capacitors to the complementary logic levels on the bitline and the bitline-bar line corresponding to a logic state to be stored in memory. The common terminal of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell to one of the two logic states.
In a read operation, the first and second transistors of the dual capacitor memory cell are enabled to couple the information stored on the first and second capacitors to the bitline and the bitline-bar line. A differential signal is generated across the bitline and the bitline-bar line by the dual capacitor memory cell. The differential signal is sensed by a sense amplifier which provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
In essence, the instant invention relates to the fabrication of an FeRAM device that is either a stand-alone device or one which is integrated onto a semiconductor chip that includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and backend processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
The following discussion is based on the concept of creating the ferroelectric capacitors in a FeRAM process module that occurs between the front end module (defined to end with the formation of tungsten, which has the chemical symbol W, contacts) and backend process module (mostly metallization). Other locations of the FeRAM process module have also been proposed. For example, if the FeRAM process module is placed over the first layer of metallization (Metal-1) then a capacitor over bitline structure can be created with the advantage that a larger capacitor can be created. One disadvantage of the approach is that either Metal-1 (the first metal layer on the chip, which is the one closest to the substrate) or local interconnect should be compatible with FeRAM process temperatures (for tungsten for example) or the FeRAM process temperature should be lowered to be compatible with standard metallization (Alxcx9c450 C, Cu and low dielectric constant materials xcx9c400 C). This location has some advantages for commodity memory purposes but has cost disadvantages for embedded memory applications.
Another possible location for the FeRAM process module is near the end of the back-end process flow. The principal advantage of this approach is that it keeps new contaminants in the FeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools. This solution is most practical if the equipment used after deposition of the first FeRAM film is dedicated to the fabrication of the FeRAM device structures and, therefore, is not shared. However, this solution has the drawback of requiring FeRAM process temperatures compatible with standard metallization structures (suggested limitations discussed above). In addition, the interconnection of the FeRAM capacitor to underlying transistors and other needs of metallization are not compatible with a minimum FeRAM cell size.
The requirements for the other locations will have many of the same concerns but some requirements will be different.
The FeRAM process module is preferably compatible with standard logic and analog device front-end process flows that include the use of tungsten contacts as the bottom contact of the capacitor. The FeRAM thermal budget must also be low enough so that it does not impact the front end structures such as the low resistance structures (which includes the tungsten plugs and silicided source/drains and gates) required by most logic devices. In addition, transistors and other front end devices, such as diodes, are sensitive to contamination. Contamination from the FeRAM process module, either direct (such as by diffusion in the chip) or indirect (cross contamination through shared equipment), should be addressed so as to avoid transistor and diode degradation. The FeRAM devices and process module should also be compatible with standard backend process flow. Therefore the FeRAM process module should have minimum degradation of logic metallization""s resistance and parasitic capacitance between metal and transistor. In addition, the FeRAM devices should not be degraded by the backend process flow with minimal, if any modification. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen degradation and most logic backend process flows utilize hydrogen and/or deuterium in many of the processes (such as in the formation of SiO2 and Si3N4, CVD tungsten deposition, SiO2 via etch, and forming gas anneals).
Commercial success of FeRAM also requires minimization of embedded memory cost. Total memory cost is primarily dependent on cell size, periphery ratio size, impact of yield, and additional process costs associated with memory. In order to have cost advantage per bit compared to standard embedded memories such as embedded DRAM and Flash it is desirable to have FeRAM cell sizes that are similar to those obtained with standard embedded memory technology. Some of the methods discussed in this patent to minimize cell size include making the process flow less sensitive to lithography misalignment, forming the capacitor directly over the contact, and using a single mask for the capacitor stack etch. Some of the methods discussed in this patent, to reduce the added process cost, may require two additional masks for the FeRAM process module and a planar capacitor which reduces the complexity of the needed processes.
Although this patent focuses on using a planar capacitor, a three dimensional capacitor using post or cup structure can be fabricated using many of the same concepts and processes. The planar structure is illustrated because it uses a simpler process and is cheaper to make. The 3D capacitor is preferred when the planar capacitor area needed for minimum charge storage considerations limits the cell size. In this situation, the capacitor area enhancement associated with the 3D configuration allows a smaller planar cell size. DRAM devices have used this approach for many years in order to reduce cell area.
An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess the first conductive material below the top surface of the dielectric layer; depositing a second conductive material in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material on the second conductive material, at least one of the second conductive material and the third conductive material acting as a diffusion barrier to prevent oxidation of the first conductive material. Preferably, second conductive material acts as the diffusion barrier and the third conductive material forms the bottom electrode of a ferroelectric capacitor, and is comprised of: TiAlN, TiSiN, TaN, TiN, CrN, CrAlN, TaSiN, ZrN, HfN, or any combination or stack thereof. The third conductive material is, preferably, comprised of: iridium, iridium oxide, or any combination or stack thereof.
In an alternative embodiment, the step of forming a second conductive material in the recess so as to have a top surface which is substantially planar and substantially coextensive with the top surface of the dielectric layer is comprised of the steps of: forming the second conductive material in the recess and on the top surface of the dielectric layer, the second conductive material filling the recess; and polishing the second conductive material to remove substantially all of the second conductive material formed on the top surface of the dielectric layer and to planarize the second conductive material formed in the recess. Preferably, the first conductive material is comprised of: doped polycrystalline silicon, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, or any combination or stack thereof, and the second conductive material is selected from the group consisting of: Ti, Ta, TaN, TiAlN, TaSiN, TiSiN, HfN, ZrN, HfAlN, CrN, TaAlN, CrAlN, WSix, WSixNy, TaSix, TiSix, Ir, Pt, Ru, Pd, Rd, doped polycrystalline silicon, undoped polycrystalline silicon, and any combination or stack thereof. The third conductive material is, preferably, comprised of a conductor selected from the group consisting of: TiAlN, TiSiN, TaN, TiN, CrN, CrAlN, TaSiN, ZrN, HfN, or any combination or stack thereof.